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EP7309 Data Sheet
FEATURES
I ARM720T Processor -- ARM7TDMI CPU -- 8 KB of four-way set-associative cache -- MMU with 64-entry TLB -- Thumb code support enabled I Ultra low power -- 90 mW at 74 MHz typical -- 30 mW at 18 MHz typical -- 10 mW in the Idle State -- <1 mW in the Standby State I Advanced audio decoder/decompression capability -- Supports bit streams with adaptive bit rates -- Allows for support of multiple audio decompression algorithms (MP3, WMA, AAC, ADPCM, Audible, etc.)
High-Performance, Low-Power System on Chip Enhanced Digital Audio Interface
OVERVIEW
The MaverickTM EP7309 is designed for ultra-low-power applications such as digital music players, internet appliances, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KB of fourway set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft(R) Windows(R) CE and Linux(R).
(cont.)
(cont.)
BLOCK DIAGRAM
Digital Audio Interface Power Management
EPB Bus
Clocks & Timers
ICE-JTAG
SERIAL PORTS
Serial Interface
ARM720T
ARM7TDMI CPU Core
Interrupts, PWM & GPIO
USER INTERFACE
(2) UARTs w/ IrDA Internal Data Bus
Boot ROM
8 KB Write Cache Buffer MMU
Bus Bridge
Keypad& Touch Screen I/F
MaverickKeyTM
SRAM & FLASH I/F
On-chip SRAM 48 KB
LCD Controller
MEMORY AND STORAGE
Copyright 2001 Cirrus Logic (All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
June '01 DS507PP1 1
EP7309 High-Performance, Low-Power System on Chip
FEATURES (cont)
I Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz I 48 KB of on-chip SRAM I MaverickKeyTM IDs -- 32-bit unique ID can be used for SDMI compliance -- 128-bit random ID I LCD controller -- Interfaces directly to a single-scan panel monochrome STN LCD -- Interfaces to a single-scan panel color STN LCD with minimal external glue logic I Full JTAG boundary scan and Embedded ICE support I Integrated Peripheral Interfaces -- 8/32/16-bit SRAM/FLASH/ROM Interface -- Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs -- Two Synchronous Serial Interfaces (SSI1, SSI2) -- CODEC Sound Interface -- 8x8 Keypad Scanner -- 27 General Purpose Input/Output pins -- Dedicated LED flasher pin from the RTC I Internal Peripherals -- Two 16550 compatible UARTs -- IrDA Interface -- Two PWM Interfaces -- Real-time Clock -- Two general purpose 16-bit timers -- Interrupt Controller -- Boot ROM I Package -- 208-Pin LQFP -- 256-Ball PBGA -- 204-Ball TFBGA I The fully static EP7309 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process
OVERVIEW (cont.)
The EP7309 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: operating, idle and standby. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal CS43L41/42/43 low-power audio DACs and the Crystal CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Simply by adding desired memory and peripherals to the highly integrated EP7309 completes a low-power system solution. All necessary interface logic is integrated onchip.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7309 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: * ARM (32-bit) and Thumb (16-bit compressed) instruction sets * Enhanced MMU for Microsoft Windows CE and other operating systems * 8 KB of 4-way set-associative cache. * Translation Look Aside Buffers with 64 Translated Entries
Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7309 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7309 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances.
Memory Interfaces
The EP7309 is equiped with a ROM/SRAM/FLASHstyle interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density.
Pin Mnemonic
nCS[5:0] A[27:0] D[31:0]
Power Management
The EP7309 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states: * Operating -- This state is the full performance state. All the clocks and peripheral logic are enabled. * Idle -- This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. * Standby -- This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor.
I/O
O O I/O O O O O O
Pin Description
Chip select out Address output Data I/O ROM expansion OP enable ROM expansion write enable Halfword access select output Word access select output Transfer direction
Pin Mnemonic
BATOK nEXTPWR nPWRFL nBATCHG
I/O
I I I I
Pin Description
Battery ok input External power supply sense input Power fail sense input Battery changed sense input
nMOE nMWE HALFWORD WORD WRITE
Table A. Power Management Pin Assignments
Table B. Static Memory Interface Pin Assignments
MaverickKeyTM Unique ID
MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure
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Digital Audio Capability
The EP7309 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7309
Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP7309 High-Performance, Low-Power System on Chip
Universal Asynchronous Receiver/Transmitters (UARTs)
The EP7309 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the RX/TX signals to/from UART 1 to enable these signals to drive an infrared communication interface directly.
Pin Mnemonic
TXD[1] RXD[1] CTS DCD DSR TXD[2] RXD[2] LEDDRV PHDIN
CODEC Interface
The EP7309 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the DAI and SSI2.
Pin Mnemonic
PCMCLK PCMOUT PCMIN PCMSYNC
I/O
O O I O
Pin Description
Serial bit clock Serial data out Serial data in Frame sync
I/O
O I I I I O I O I
Pin Description
UART 1 transmit UART 1 receive UART 1 clear to send UART 1 data carrier detect UART 1 data set ready UART 2 transmit UART 2 receive Infrared LED drive output Photo diode input
Table E. CODEC Interface Pin Assignments Note: See Table Q on page 7 for information on pin multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is available for both master and slave mode communications. The SSI2 unit shares the same pins as the DAI and CODEC interfaces through a multiplexer. * * * * Synchronous clock speeds of up to 512 kHz Separate 16 entry TX and RX half-word wide FIFOs Half empty/full interrupts for FIFOs Separate RX and TX frame sync signals for asymmetric traffic
Table C. Universal Asynchronous Receiver/Transmitters Pin Assignments
Digital Audio Interface (DAI)
The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal CS43L41/42/43 low-power audio DACs and the Crystal CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions.
Pin Mnemonic
SCLK SDOUT SDIN LRCK MCLKIN MCLKOUT
Pin Mnemonic
SSICLK SSITXDA SSIRXDA
I/O
I/O O I I/O I/O
Pin Description
Serial bit clock Serial data out Serial data in Transmit frame sync Receive frame sync
I/O
O O I O I O
Pin Description
Serial bit clock Serial data out Serial data in Sample clock Master clock input Master clock output
SSITXFR SSIRXFR
Table F. SSI2 Interface Pin Assignments Note: See Table Q on page 7 for information on pin multiplexes.
Table D. DAI Interface Pin Assignments Note: See Table Q on page 7 for information on pin multiplexes.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Synchronous Serial Interface
* ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation) * Selectable serial clock polarity
Pin Mnemonic
ADCLK ADCIN ADCOUT nADCCS SMPCLK
I/O
O I O O O
Pin Description
SSI1 ADC serial clock SSI1 ADC serial input SSI1 ADC serial output SSI1 ADC chip select SSI1 ADC sample clock
* Column outputs can be individually set high with the remaining bits left at high-impedance * Column outputs can be driven all-low, all-high, or allhigh-impedance * Keyboard interrupt driven by OR'ing together all Port A bits * Keyboard interrupt can be used to wake up the system * 8x8 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic
Pin Mnemonic
COL[7:0]
I/O
O
Pin Description
Keyboard scanner column drive
Table G. Serial Interface Pin Assignments
Table I. Keypad Interface Pin Assignments
LCD Controller
A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is programmable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM. * Interfaces directly to a single-scan panel monochrome STN LCD * Interfaces to a single-scan panel color STN LCD with minimal external glue logic * Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments * Video frame buffer size programmable up to 128 KB * Bits per pixel of 1, 2, or 4 bits
Interrupt Controller
When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7309 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. * Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.) * Routes interrupt sources to the ARM720T's IRQ or FIQ (Fast IRQ) inputs * Five dedicated off-chip interrupt lines operate as level sensitive interrupts
.
Pin Mnemonic
CL1 CL2 DD[3:0] FRM M
I/O
O O O O O
Pin Description
LCD line clock LCD pixel clock out LCD serial display data bus LCD frame synchronization pulse LCD AC bias drive
Pin Mnemonic
nEINT[2:1] EINT[3] nEXTFIQ nMEDCHG/nBROM (Note)
I/O
I I I I
Pin Description
External interrupt External interrupt External Fast Interrupt input Media change interrupt input
Table H. LCD Interface Pin Assignments
Table J. Interrupt Controller Pin Assignments Note: Pins are multiplexed. See Table R on page 7 for more information.
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the EP7309. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state.
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Real-Time Clock
The EP7309 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
EP7309 High-Performance, Low-Power System on Chip
* Driven byan external 32.768 kHz crystal oscillator
Pin Mnemonic Pin Mnemonic
RTCIN RTCOUT VDDRTC VSSRTC
I/O
I I (Note) I/O I/O (Note) I/O I I
Pin Description
GPIO port A GPIO port B GPIO port D GPIO port D GPIO port D GPIO port E GPIO port E
Pin Description
Real-Time Clock Oscillator Input
PA[7:0] PB[7:0] PD[0]/LEDFLSH
Real-Time Clock Oscillator Output PD[5:1] Real-Time Clock Oscillator Power PD[7:6]/SDQM[1:0] Real-Time Clock Oscillator Ground PE[1:0]/BOOTSEL[1:0] (Note) PE[2]/CLKSEL (Note)
Table K. Real-Time Clock Pin Assignments
PLL and Clocking
* Processor and Peripheral Clocks operate from a single 3.6864 MHz crystal or external 13 MHz clock * Programmable clock speeds allow the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at 36 MHz when the processor is set to 36, 49 or 74 MHz
Table N. General Purpose Input/Output Pin Assignments Note: Pins are multiplexed. See Table R on page 7 for more information.
Hardware debug Interface
* Full JTAG boundary scan and Embedded ICE support
Pin Mnemonic
MOSCIN MOSCOUT VDDOSC VSSOSC
Pin Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
Pin Mnemonic
TCLK TDI TDO nTRST TMS
I/O
I I O I I
Pin Description
JTAG clock JTAG data input JTAG data output JTAG async reset input JTAG mode select
Table L. PLL and Clocking Pin Assignments
DC-to-DC converter interface (PWM)
* Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter
Table O. Hardware Debug Interface Pin Assignments
LED Flasher
A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a PDA. * * * * Software adjustable flash period and duty cycle Operates from 32 kHz RTC clock Will continue to flash in IDLE and STANDBY states 4 mA drive current
Pin Mnemonic
DRIVE[1:0] FB[1:0]
I/O
I/O I
Pin Description
PWM drive output PWM feedback input
Table M. DC-to-DC Converter Interface Pin Assignments
Timers
* Internal (RTC) timer * Two internal 16-bit programmable hardware countdown timers
Pin Mnemonic
PD[0]/LEDFLSH (Note)
I/O
O
Pin Description
LED flasher driver
General Purpose Input/Output (GPIO)
* Three 8-bit and one 3-bit GPIO ports * Supports scanning keyboard matrix
Note:
Table P. LED Flasher Pin Assignments Pins are multiplexed. See Table R on page 7 for more information.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH.
Pin Mnemonic
SSITXFR SSIRXFR BUZ
I/O
I/O I O
DAI
LRCK MCLKIN MCLKOUT
SSI2
SSITXFR SSIRXFR
CODEC
PCMSYNC p/u
Packaging
The EP7309 is available in a 208-pin LQFP package, 256ball PBGA package or a 204-ball TFBGA package.
Table Q. DAI/SSI2/CODEC Pin Multiplexing
Pin Multiplexing
The following table shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7309 User's Manual for more information).
Pin Mnemonic
SSICLK SSITXDA SSIRXDA
The following table shows the pins that have been multiplexed in the EP7309.
Signal
RUN nMEDCHG PD[0] PE[1:0] PE[2]
Block
System Configuration Interrupt Controller GPIO GPIO GPIO
Signal
CLKEN nBROM LEDFLSH BOOTSEL[1:0] CLKSEL
Block
System Configuration Boot ROM select LED Flasher System Configuration System Configuration
I/O
I/O O I
DAI
SCLK SDOUT SDIN
SSI2
SSICLK SSITXDA SSIRXDA
CODEC
PCMCLK PCMOUT PCMIN
Table Q. DAI/SSI2/CODEC Pin Multiplexing
Table R. Pin Multiplexing
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Copyright 2001 Cirrus Logic (All Rights Reserved)
7
EP7309 High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7309 completes a low-power system solution. All necessary interface logic is integrated on-chip.
CRYSTAL CRYSTAL
MOSCIN RTCIN
DD[0-3] CL1 CL2 FRM M COL[0-7]
LCD
KEYBOARD
nCS[4] PB0 EXPCLK PA[0-7] PB[0-7] PD[0-7] D[0-31] PE[0-2] nPOR nPWRFL BATOK nEXTPWR nBATCHG RUN WAKEUP DRIVE[0-1] FB[0-1] SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR LEDDRV PHDIN CS[n] WORD RXD1/2 TXD1/2 DSR CTS DCD ADCCLK nADCCS ADCOUT ADCIN SMPCLK
EP7309
PC CARD SOCKET
PC CARD CONTROLLER
A[0-27] nMOE WRITE
POWER SUPPLY UNIT AND COMPARATORS
DC INPUT
BATTERY
nCS[0] nCS[1]
DC-TO-DC CONVERTERS
x16 FLASH x16 FLASH
x16 FLASH x16 FLASH
CODEC/SSI2/ DAI
IR LED AND PHOTODIODE
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
2x RS-232 TRANSCEIVERS
nCS[2] nCS[3]
ADDITIONAL I/O
BUFFERS AND LATCHES
ADC
DIGITIZER
LEDFLSH
Figure 1. A Maximum EP7309 Based System Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Pad Input Current Storage Temperature, No Power 2.9 V 3.6 V
10 mA/pin; 100 mA cumulative
-40C to +125C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Input / Output Voltage Operating Temperature 2.5 V 0.2 V 2.3 V - 3.6 V O-I/O supply voltage Extended -20C to +70C; Commercial 0C to +70C; Industrial -40C to +85C
DC Characteristics
All characteristics are specified at VDD = 2.5 V and VSS = 0 V over an operating temperature of 0C to +70C for all frequencies of operation. The current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation with the PLL switched "on."
Symbol
VIH VIL VT+
Parameter
CMOS input high voltage CMOS input low voltage Schmitt trigger positive going threshold Schmitt trigger negative going threshold Schmitt trigger hysteresis CMOS output high voltagea
Min
0.65 x VDDIO -0.3 1.6 (Typ)
Typ
Max
VDDIO + 0.3 0.25 x VDDIO 2.0
Unit
V V V
Conditions
VDDIO = 2.5 V VDDIO = 2.5 V
VTVhst
0.8 0.1 VDD - 0.2 2.5 2.5
1.2 (Typ) 0.4
V V V V V VIL to VIH IOH = 0.1 mA IOH = 4 mA IOH = 12 mA IOL = -0.1 mA IOL = -4 mA IOL = -12 mA VIN = VDD or GND VOUT = VDD or GND
VOH
Output drive 1a Output drive 2a CMOS output low voltagea
VOL
Output drive 1a Output drive 2a
0.3 0.5 0.5 1.0 25 8 100 10.0
V V V A A pF
IIN IOZ CIN
Input leakage current Bidirectional 3-state leakage currentb c Input capacitance
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Copyright 2001 Cirrus Logic (All Rights Reserved)
9
EP7309 High-Performance, Low-Power System on Chip
Symbol
COUT CI/O
Parameter
Output capacitance Transceiver capacitance
Min
8 8
Typ
Max
10.0 10.0
Unit
pF pF
Conditions
Standby current consumption IDDstandby Core, Osc, RTC @2.5 V I/O @ 3.3 V
TBD TBD
300
A
Only 32 kHz oscillator running, Cache disabled, all other I/O static, VIH = VDD 0.1 V, VIL = GND 0.1 V Both oscillators running, CPU static, Cache disabled, LCD refresh active, VIH = VDD 0.1 V, VIL = GND 0.1 V At 13 MHz All system active, running typical program, cache disabled, and LCD inactive Minimum standby voltage for state retention and RTC operation only
IDDidle
Idle current consumption Core, Osc, RTC @2.5 V I/O @ 2.5 V
TBD TBD
4.2
mA
Operating current consumption IDDoperatin Core, Osc, RTC @2.5 V I/O @ 3.3 V
TBD TBD
mA
VDDstandby Standby supply voltage a. b. c. Note: See Table S on page 23.
TBD
V
Assumes buffer has no pull-up or pull-down resistors. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven. 1) All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V. 2) The RTC of the EP7309 should be brought up at room temperature. This is required because the RTC OSC will NOT function properly if it is brought up at -40C. Once operational, it will continue to operate down to -20C extended and 0C commercial. 3) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be compatible with 3.3 V powered external logic. 4) Pull-up current = 50 A typical at VDD = 3.3 V.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at VDD = 2.3 - 2.7 V and VSS = 0 V over an operating temperature of 0C to +70C. Those characteristics marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
11
EP7309 High-Performance, Low-Power System on Chip
Static Memory
Figure 2 through Figure 5 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes.
Parameter
EXPCLK rising edge to nCS assert delay time EXPCLK falling edge to nCS deassert hold time EXPCLK rising edge to A assert delay time EXPCLK falling edge to A deassert hold time EXPCLK rising edge to nMWE assert delay time EXPCLK rising edge to nMWE deassert hold time EXPCLK falling edge to nMOE assert delay time EXPCLK falling edge to nMOE deassert hold time EXPCLK falling edge to HALFWORD deassert delay time EXPCLK falling edge to WORD assert delay time EXPCLK rising edge to data valid delay time EXPCLK falling edge to data invalid delay time Data setup to EXPCLK falling edge time EXPCLK falling edge to data hold time EXPCLK rising edge to WRITE assert delay time EXPREADY setup to EXPCLK falling edge time EXPCLK falling edge to EXPREADY hold time
Symbol
tCSd tCSh tAd tAh tMWd tMWh tMOEd tMOEh tHWd tWDd tDv tDnv tDs tDh tWRd tEXs tEXh
Min
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Typ
8 4 4 8 4 4 4 4 4 4 20 8 8 -
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK tCSd nCS tAd A tCSh
nMWE tMOEd nMOE tHWd HALF WORD tWDd WORD tDs D tEXs EXPRDY tWRd WRITE tEXh tDh tMOEh
Figure 2. Static Memory Single Read Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
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Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP7309 High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK tCSd nCS tAd A tMWd nMWE tMWh tCSh
nMOE tHWd HALF WORD
tWDd WORD tDv D tEXs EXPRDY tEXh
WRITE
Figure 3. Static Memory Single Write Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions.
14
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK tCSd nCS tAd A tAh tAh tAh tCSh
nMWE tMOEd nMOE tHWd HALF WORD tMOEh
WORD
tWDd tDs tDh tDs tDh tDs tDh tDs tDh
D tEXs EXPRDY tWRd WRITE tEXh
Figure 4. Static Memory Burst Read Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
15
EP7309 High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK tCSd nCS tAd A tMWd nMWE tMWh tMWd tMWh tMWd tMWh tMWd tMWh tAh tAh tAh tCSh
nMOE tHWd HALF WORD
WORD
tWDd tDv tDnv tDv tDnv tDv tDnv tDv
D tEXs EXPRDY tEXh
WRITE
Figure 5. Static Memory Burst Write Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions.
16
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time
Symbol
tCd tINs tINh tOvd tOd
Min
TBD TBD TBD TBD TBD
Max
TBD TBD TBD TBD TBD
Unit
ns ns ns ns ns
ADC CLK
tCd
nADC CSS
tINs tINh
ADCIN
tOvd tOd
ADC OUT
Figure 6. SSI1 Interface Timing Measurement
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
17
EP7309 High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
SSICLK period (slave mode) SSICLK high time SSICLK low time SSICLK rise/fall time SSICLK rising edge to RX and/or TX frame sync high time SSICLK rising edge to RX and/or TX frame sync low time SSIRXFR and/or SSITXFR period SSIRXDA setup to SSICLK falling edge time SSIRXDA hold from SSICLK falling edge time SSICLK rising edge to SSITXDA data valid delay time SSITXDA valid time
Symbol
tclk_per tclk_high tclk_low tclkrf tFRd tFRa tFR_per tRXs tRXh tTXd tTXv
Min
0 925 925
Max
512 1025 1025 7 528 448
Unit
ns ns ns ns ns ns ns ns ns
750 30 40 80
ns ns
tclk_per
tclk_high
tclk_low
SSI CLK
tclkrf tFRd tFRa tFR_per
SSIRXFR/ SSITXFR
tRXh tRXs
SSI RXDA
tTXd
D7
D2
D1
D0
SSI TXDA
D7
tTXv
D2
D1
D0
Figure 7. SSI2 Interface Timing Measurement
18
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
LCD Interface
Parameter
CL[1] falling to CL[2] falling time LCD CL[2] low time LCD CL[2] high time CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time LCD CL[1] high time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time
Symbol
tclk tclk_low tclk_high tCL1d tCL2d tCL2h tFRMd tMd tDDd
Min
200 80 80 0 80 80 300
Max
6,950 3,475 3,475 25 3,475 3,475 10,425 20 20
Unit
ns ns ns ns ns ns ns ns ns
- 10 - 10
tclk CL[2] tCL1d CL[1] tFRMd FRM tMd M tDDd DD [3:0] tCL2h tCL2d
tclk_low
tclk_high
Figure 8. LCD Controller Timing Measurement
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
19
EP7309 High-Performance, Low-Power System on Chip
JTAG
Parameter
TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance
Symbol
tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz
Min
100 50 50 20 45 -
Max
25 25 25
Units
ns ns ns ns ns ns ns ns
tclk_per tclk_high TCK tJPs TMS tJPh tclk_low
TDI tJPzx TDO tJPco tJPxz
Figure 9. JTAG Timing Measurement
20
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011)
27.80 (1.094) 28.20 (1.110)
29.60 (1.165) 30.40 (1.197)
EP7309
208-Pin LQFP
0.50 (0.0197) BSC
Pin 1 Indicator
Pin 208 Pin 1
0.45 (0.018) 0.75 (0.030)
1.35 (0.053) 1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006)
0 MIN 7 MAX
Figure 10. 208-Pin LQFP Package Outline Drawing Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin locations, please see Figure 11. For pin descriptions see the EP7309 User's Manual.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
21
EP7309 High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
nURESET nMEDCHG/nBROM nPOR BATOK nEXTPWR nBATCHG D[7] VSSIO A[7] D[8] A[8] D[9] A[9] D[10] A[10] D[11] VSSIO VDDIO A[11] D[12] A[12] D[13] A[13] D[14] A[14] D[15] A[15] D[16] A[16] D[17] A[17] nTRST VSSIO VDDIO D[18] A[18 D[19] A[19] D[20] A[20] VSSIO D[21] A[21] D[22] A[22] D[23] A[23] D[24] VSSIO VDDIO A[24] HALFWORD 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP nPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE VSSIO VDDIO CL[2] CL[1] FRM M DD[3] DD[2] VSSIO DD[1] DD[0]
N/C N/C N/C N/C
VDDIO VSSIO
N/C N/C
nMWE nMOE VSSIO nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
EP7309
208-Pin LQFP
(Top View)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
D[25] A[25] D[26] A[26] D[27] A[27] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE nADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFLSH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6] PD[7]
Note:
1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7212 and the EP7309 are bolded.
22
nCS[5] VDDIO VSSIO EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD DSR nTEST[1] nTEST[0] EINT[3] nEINT[2] nEINT[1] nEXTFIQ PE[2]/CLKSEL PE[1]BOOTSEL[1] PE[0]BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 11. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table S. 208-Pin LQFP Numeric Pin Listing Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Signal
nCS[5] VDDIO VSSIO EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY2 PB[0]/PRDY1 VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD
Type
O Pad Pwr Pad Gnd I/O Out Out O I O I
Strength
1
Reset State
High
Pin No.
38 39 40
Signal
DSR nTEST[1] nTEST[0] EINT[3] nEINT[2] nEINT[1] nEXTFIQ PE[2]/CLKSEL PE[1]/ BOOTSEL[1] PE[0]/ BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C PD[7] PD[6] PD[5] PD[4] VDDIO TMS PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSICLK VSSIO SSITXFR SSITXDA SSIRXDA SSIRXFR ADCIN nADCCS VSSCORE VDDCORE VSSIO
Type
I I I I I I I I/O I/O I/O RTC Gnd O I RTC power
Strength
Reset State
With p/u* With p/u*
1 1 1 1 1 1 High Low Low Low
41 42 43 44 45 46 47
1 1 1
Input Input Input
I Pad Gnd I/O I/O I/O I/O I/O I/O I/O I/O Pad Pwr O I/O I/O I/O I/O I/O I/O I/O I/O O O Pad Gnd I I I I
with p/u* 48 1 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input 49 50 51 52 53 54 55 56 57 1 1 1 1 1 1 1 1 1 1 1 1 Three state Input Input Input Input Input Input Input Input Low High High 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
I/O I/O I/O I/O Pad Pwr I I/O I/O I/O I/O I/O Pad Gnd I/O O I I/O I O Core Gnd Core Pwr Pad Gnd
1 1 1 1
Low Low Low Low
with p/u* 1 1 1 1 1 Low Low Low Low Input
1 1
Low Low
Input
1
High
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
23
EP7309 High-Performance, Low-Power System on Chip
Table S. 208-Pin LQFP Numeric Pin Listing (Continued) Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No.
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
Signal
VDDIO DRIVE[1] DRIVE[0] ADCCLK ADCOUT SMPCLK FB[1] VSSIO FB[0] COL[7] COL[6] COL[5] COL[4] COL[3] COL[2] VDDIO TCLK COL[1] COL[0] BUZ D[31] D[30] D[29] D[28] VSSIO A[27] D[27] A[26] D[26] A[25] D[25] HALFWORD A[24] VDDIO VSSIO D[24] A[23]
Type
Pad Pwr I/O I/O O O O I Pad Gnd I O O O O O O Pad Pwr I O O O I/O I/O I/O I/O Pad Gnd O I/O O I/O O I/O O O Pad Pwr Pad Gnd I/O O
Strength
Reset State
Pin No.
111
Signal
D[23] A[22] D[22] A[21] D[21] VSSIO A[20] D[20] A[19] D[19] A[18] D[18] VDDIO VSSIO nTRST A[17] D[17] A[16] D[16] A[15] D[15] A[14] D[14] A[13] D[13] A[12] D[12] A[11] VDDIO VSSIO D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7]
Type
I/O O I/O O I/O Pad Gnd O I/O O I/O O I/O Pad Pwr Pad Gnd I O I/O O I/O O I/O O I/O O I/O O I/O O Pad Pwr Pad Gnd I/O O I/O O I/O O I/O O
Strength
1 1 1 1 1
Reset State
Low Low Low Low Low
2 2 1 1 1
High / Low High / Low Low Low Low
112 113 114 115 116 117 118 119 120
1 1 1 1 1 1
Low Low Low Low Low Low
1 1 1 1 1 1
High High High High High High
121 122 123 124 125 126 127 128
1 1 1 1 1 1 1 1 1 1 1 1 1
Low Low Low Low Low Low Low Low Low Low Low Low Low
1 1 1 1 1 1 1
High High Low Low Low Low Low
129 130 131 132 133 134 135 136
2 1 2 1 2 1 1 1
Low Low Low Low Low Low Low Low -- --
137 138 139 140 141 142 143 144 145 146 147 148
1 1 1 1 1 1 1 1
Low Low Low Low Low Low Low Low
1 1
Low Low
24
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table S. 208-Pin LQFP Numeric Pin Listing (Continued) Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No.
149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
Signal
VSSIO D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/ nBROM nURESET VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP nPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSS CORE VDD CORE VSSIO VDDIO CL[2] CL[1] FRM
Type
Pad Gnd I/O I I I I I I Osc Pwr Osc Osc Osc Gnd I I O I/O Out I/O Pad Pwr Pad Gnd O I/O O I/O O Pad Gnd I/O O I/O O I/O Core Gnd Core Pwr Pad Gnd Pad Pwr O O O
Strength
Reset State
Pin No.
187
Signal
M DD[3] DD[2] VSSIO DD[1] DD[0] N/C N/C N/C N/C VDDIO VSSIO N/C N/C nMWE nMOE VSSIO nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
Type
O I/O I/O Pad Gnd I/O I/O O O I/O I/O Pad Pwr Pad Gnd I/O I/O O O Pad Gnd O O O O O
Strength
1 1 1
Reset State
Low Low Low
1
Low
188 189 190 191
1 1 1 1 2 2
Low Low High High Low Low
Schmitt
192 193 194
Schmitt
195 196 197 198 199
2 2 1 1
Low Low High High
Schmitt
200 201 Low Low Low Low
1 1 1 1
202 203 204 205 206 207
1 1 1 1 1
High High High High High
1 1 2 1 2
Low Low Low Low Low
208
*With p/u' means with internal pull-up on the pin.
1 2 1 2 1
Low Low Low Low Low
1 1 1
Low Low Low
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
25
EP7309 High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
TOP VIEW A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y
O0.08 M C
BOTTOM VIEW A1 CORNER
A B C D E F G H J K L M N P R T U V W Y 0.65 12.35
O0.15 M C A B O0.25~0.35(204X)
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
130.05
A
12.35
0.65
B 0.530.05 0.20 C
0.15(4X) C
130.05
0.10 C
Ball Pitch : 0.65
0.36 0.20~0.30 C 1.20 MAX.
Substrate Thickness : 0.36 Mold Thickness : 0.53
SEATING PLANE
Ball Diameter : 0.3
Figure 12. 204-Ball TFBGA Package
26
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1 A VDDR 2 EXPCLK 3 nCS3 4 5 6 N/C 7 N/C 8 DD2 9 FRM 10 CL1 11 GNDD 12 D1 13 A2 14 D4 15 A5 16 17 18 GNDR 19 GNDR 20 GNDR A
nCS1 nMWE
nPWRFL MOSCOUT
B WORD
VDDR
nCS5
nCS2
nMOE
N/C
N/C
DD1
M
CL2
D0
A1
D3
A4
D6
WAKEUP MOSCIN
GNDR
GNDR nURESET B
C
RUN/ EXPRDY VDDR CLKEN PB7 RXD2 VDDR
nCS4
nCS0
N/C
N/C
DD0
DD3
VDDD
A0
D2
A3
D5
A6
GNDO
VDDO
GNDR
BATOK
nPOR
C
D
GNDR
nBATCHG
A7
D
E
PB4
TXD2
WRITE
nMEDCHG nEXTPWR /nBROM D7 A8
D9
E
F
PB3
PB6
TDI
D10
F
G
PB1
PB2
PB5
D8
A9
D11
G
H
PA7
TDO
PB0
A10
D12
A12
H
J
PA4
PA5
PA6
A11
D13
A13
J
K
PA1
PA2
VDDR
D14
A14
D15
K
L
TXD1
LEDDRV
PA3
VDDR
D16
A16
L
M RXD1
CTS
PA0
A15
A17
nTRST M
N
DSR
nTEST1 PHDIN
D17
D19
A18
N
P EINT3
nEINT2
DCD
D18
A20
D20
P
R nEXTFIQ PE1/ BOOT SEL1
PE2/ nTEST0 CLKSEL PE0/ BOOT SEL0
A19
D22
A21
R
T
nEINT1
D21
D23
A22
T
U GNDC
RTCOUT RTCIN
HALF WORD PD7 PD4 PD2 SSICLK SSIRXDA nADCCS VDDR ADCCLK COL7 COL4 TCLK BUZ D29 A26 VDDR
D24
A23
U
V VDDC
GNDR
GNDR
VDDR
A24
V
W GNDR
GNDR
GNDR
PD6
TMS
PD1
SSITXFR SSIRXFR GNDD1 DRIVE1 ADCOUT
FB0
COL5 COL2
COL0
D30
A27
D26
VDDR
D25
W
Y GNDR
GNDR
GNDR
PD5
PD3
PD0/ LED SSITXDA ADCIN FLSH
VDD1 DRIVE0 SMPLCK
FB1
COL6 COL3
COL1
D31
D28
D27
A25
VDDR
Y
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
27
EP7309 High-Performance, Low-Power System on Chip
TFBGA Ball List
Table T. 204-Ball TFBGA Ball List Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
U2.1 U2.2 U2.3 U2.4 U2.5 U2.6 U2.7 U2.8 U2.9 U2.10 U2.11 U2.12 U2.13 U2.14 U2.15 U2.16 U2.17 U2.18 U2.19 U2.20 U2.21 U2.22 U2.23 U2.24 U2.25 U2.26 U2.27 U2.28 U2.29 U2.30 U2.31 U2.32 U2.33 U2.34 U2.35 U2.36 U2.37
Bond Pad Package Ball
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 B3 Y20 B18 A2 B1 E3 C1 C2 E2 D2 F3 B18 D1 F2 G3 E1 F1 G2 G1 H3 Y20 H2 H1 J3 J2 J1 L3 K2 K1 M3 L2 L1 B18 N3 M2 M1 P3
Signal
nCS5 VDDR GNDR EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD2 RXD2 TDI GNDR PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VDDR TDO PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 LEDDRV TXD1 GNDR PHDIN CTS RXD1 DCD
Die Pad
U2.38 U2.39 U2.40 U2.41 U2.42 U2.43 U2.44 U2.45 U2.46 U2.47 U2.48 U2.49 U2.50 U2.51 U2.53 U2.54 U2.55 U2.56 U2.57 U2.58 U2.59 U2.60 U2.61 U2.62 U2.63 U2.64 U2.65 U2.66 U2.67 U2.68 U2.69 U2.70 U2.71 U2.72 U2.73 U2.74 U2.75 U2.76
Bond Pad Package Ball
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 N1 N2 R3 P1 P2 T3 R1 R2 T1 T2 U1 U2 U3 V1 V4 W4 Y4 V5 L18 W5 Y5 V6 W6 Y6 V7 D18 W7 Y7 V8 W8 Y8 V9 W9 Y9 W3 V10 L18 W10
Signal
DSR nTEST1 nTEST0 EINT3 nEINT2 nEINT1 nEXTFIQ PE2/CLKSEL PE1/BOOTSEL1 PE0/BOOTSEL0 GNDC RTCOUT RTCIN VDDC PD7 PD6 PD5 PD4 VDDR TMS PD3 PD2 PD1 PD0/LEDFLSH SSICLK GNDR SSITXFR SSITXDA SSIRXDA SSIRXFR ADCIN nADCCS GNDD1 VDD1 GNDR VDDR VDDR DRIVE1
28
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued) Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
U2.77 U2.78 U2.79 U2.80 U2.81 U2.82 U2.83 U2.84 U2.85 U2.86 U2.87 U2.88 U2.89 U2.90 U2.91 U2.92 U2.93 U2.94 U2.95 U2.96 U2.97 U2.98 U2.99 U2.100 U2.101 U2.102 U2.103 U2.104 U2.105 U2.106 U2.107 U2.108 U2.109 U2.110 U2.111 U2.112 U2.113 U2.114 U2.115
Bond Pad Package Ball
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Y10 V11 W11 Y11 Y12 Y3 W12 V12 Y13 W13 V13 Y14 W14 A1 V14 Y15 W15 V15 Y16 W16 V16 Y17 Y3 W17 Y18 V17 W18 Y19 W20 U18 V20 A1 Y3 U19 U20 T19 T20 R19 R20
Signal
DRIVE0 ADCCLK ADCOUT SMPLCK FB1 GNDR FB0 COL7 COL6 COL5 COL4 COL3 COL2 VDDR TCLK COL1 COL0 BUZ D31 D30 D29 D28 GNDR A27 D27 A26 D26 A25 D25 HALFWORD A24 VDDR GNDR D24 A23 D23 A22 D22 A21
Die Pad
U2.116 U2.117 U2.118 U2.119 U2.120 U2.121 U2.122 U2.123 U2.124 U2.125 U2.126 U2.127 U2.128 U2.129 U2.130 U2.131 U2.132 U2.133 U2.134 U2.135 U2.136 U2.137 U2.138 U2.139 U2.140 U2.141 U2.142 U2.143 U2.144 U2.145 U2.146 U2.147 U2.148 U2.149 U2.150 U2.151 U2.152 U2.153 U2.154
Bond Pad Package Ball
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 T18 Y3 P19 P20 R18 N19 N20 P18 A1 Y3 M20 M19 N18 L20 L19 M18 K20 K19 K18 J20 J19 H20 H19 J18 K3 Y3 G20 H18 F20 G19 E20 F19 G18 D20 Y3 F18 D19 E19 C19
Signal
D21 GNDR A20 D20 A19 D19 A18 D18 VDDR GNDR nTRST A17 D17 A16 D16 A15 D15 A14 D14 A13 D13 A12 D12 A11 VDDR GNDR D11 A10 D10 A9 D9 A8 D8 A7 GNDR D7 nBATCHG nEXTPWR BATOK
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
29
EP7309 High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued) Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
U2.155 U2.156 U2.157 U2.158 U2.159 U2.160 U2.161 U2.162 U2.163 U2.164 U2.165 U2.166 U2.167 U2.168 U2.169 U2.170 U2.171 U2.172 U2.173 U2.174 U2.175 U2.176 U2.177 U2.178 U2.179 U2.180 U2.181 U2.182 U2.183 U2.184 U2.185 U2.186 U2.187 U2.188 U2.189 U2.190 U2.191 U2.192 U2.193
Bond Pad Package Ball
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 C20 E18 B20 C17 B17 A17 C16 B16 A16 C15 B15 A15 C14 A1 Y3 B14 A14 C13 B13 A13 Y3 C12 B12 A12 C11 B11 A11 C10 Y3 Y20 B10 A10 A9 B9 C9 A8 Y3 B8 C8
Signal
nPOR nMEDCHG/nBROM nURESET VDDO MOSCIN MOSCOUT GNDO WAKEUP nPWRFL A6 D6 A5 D5 VDDR GNDR A4 D4 A3 D3 A2 GNDR D2 A1 D1 A0 D0 GNDD VDDD GNDR VDDR CL2 CL1 FRM M DD3 DD2 GNDR DD1 DD0
Die Pad
U2.194 U2.195 U2.196 U2.197 U2.198 U2.199 U2.200 U2.201 U2.202 U2.203 U2.204 U2.205 U2.206 U2.207 U2.208 U2.209
Bond Pad Package Ball
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A7 B7 C7 A6 V18 B18 B6 C6 A5 B5 B18 C5 A4 B4 A3 C4 A1 B2 C3 D3 K3 L18 V18 V19 W19 Y20 A18 A19 A20 B18 B19 C18 D18 V2 V3 W1 W2 W3
Signal
N/C N/C N/C N/C VDDR GNDR N/C N/C nMWE nMOE GNDR nCS0 nCS1 nCS2 nCS3 nCS4 VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR
30
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
Bond Pad Package Ball
Y1 Y2 Y3
Signal
GNDR GNDR GNDR
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
Figure 13. 256-Ball PBGA Package Note: 1) For pin locations see Table U. 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
31
EP7309 High-Performance, Low-Power System on Chip
0.85 (0.034) 0.05 (.002) 17.00 (0.669) 0.20 (.008) Pin 1 Corner 15.00 (0.590) 0.20 (.008) 30 TYP 0.40 (0.016) 0.05 (.002)
D1
Pin 1 Indicator 17.00 (0.669) 0.20 (.008)
E1
15.00 (0.590) 0.20 (.008)
2 Layer 0.36 (0.014) 0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669) 1.00 (0.040) 1.00 (0.040) REF
16 15 14 13 12 11 10 9 8 7
Pin 1 Corner
E
65 432 1
1.00 (0.040) REF
1.00 (0.040)
A B C D E F G H J K L M N P R T
BOTTOM VIEW
17.00 (0.669)
0.50 R 3 Places
JEDEC #: MO-151 Ball Diameter: 0.50 mm 0.10 mm 17 17 1.61 mm body
32
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View))
1 A VDDIO 2 nCS[4] 3 nCS[1] 4 N/C 5 N/C 6 DD[1] 7 M 8 VDDIO 9 D[0] 10 D[2] 11 A[3] 12 VDDIO 13 A[6] 14 15 16 VSSIO A
MOSCOUT VDDOSC
B
nCS[5]
VDDIO
nCS[3]
nMOE
VDDIO
N/C
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET B
C
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR C
D
WRITE
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE
N/C
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO nMEDCHG/ nBROM nBATCHG
VSSIO
D[7]
D[8]
D
E
RXD[2]
PB[7]
TDI
WORD
VSSIO RUN/ CLKEN PB[6]
nCS[0]
N/C
FRM
A[0]
D[5]
VSSOSC
VSSIO
VDDIO
D[9]
D[10]
E
F
PB[5]
PB[3]
VSSIO
TXD[2]
VSSIO
N/C
DD[3]
A[1]
D[6]
VSSRTC
BATOK
VSSIO
D[11]
VDDIO
F
G
PB[1]
VDDIO
TDO
PB[4]
VSSRTC
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
G
H
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]
VSSIO
D[14]
D[15]
H
J
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
CTS
VSSRTC
VSSRTC
A[17]
A[16]
A[15]
A[14]
nTRST
D[16]
D[17]
J
K LEDDRV
PHDIN
VSSIO
DCD
nTEST[1] PE[2]/ CLKSEL TMS
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
D[20]
D[19]
D[18]
VSSIO
VDDIO
VDDIO
K
L
RXD[1]
DSR
VDDIO
nEINT[1] PE[0]/ BOOTSEL[0] VDDIO
VSSRTC
PD[0]/ VSSRTC LEDFLSH SSITXFR DRIVE[1]
COL[6]
D[31]
VSSRTC
A[22]
A[21]
VSSIO
A[18]
A[19]
L
M nTEST[0]
nEINT[2]
VDDIO
VDDIO
FB[0]
COL[0]
D[27]
VSSIO
A[23]
VDDIO
A[20]
D[21]
M
N nEXTFIQ
PE[1]/ VSSIO BOOTSEL[1] RTCOUT VSSIO
PD[5]
PD[2]
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
D[26]
HALFWORD
VSSIO
D[22]
D[23]
N
P VSSRTC
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
VDDIO
P
R
RTCIN
VDDIO
PD[4]
PD[1]
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
A[27]
A[25]
VDDIO
A[24]
R
T VDDRTC
PD[7]
PD[6]
PD[3]
SSICLK
SSIRXFR VDDCORE DRIVE[0]
FB[1]
COL[5]
VDDIO
BUZ
D[28]
A[26]
D[25]
VSSIO
T
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table U. 256-Ball PBGA Ball Listing
Ball Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Name VDDIO nCS[4] nCS[1] N/C N/C DD[1] M VDDIO D[0] D[2] A[3] Type Pad power O O O O O O Pad power I/O I/O O LCD serial display data LCD AC bias drive Digital I/O power, 3.3V Data I/O Data I/O System byte address Description A12 Digital I/O power, 3.3V A13 Chip select out A14 Chip select out A15 A16 B1 B2 B3 B4 B5 B6 VDDOSC VSSIO nCS[5] VDDIO nCS[3] nMOE VDDIO N/C Oscillator power Oscillator power in, 2.5V MOSCOUT O Main oscillator out A[6] O System byte address VDDIO Pad power Digital I/O power, 3.3V
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
Pad ground I/O ground O Pad power O O Pad power O Chip select out I/O ground Chip select out ROM, expansion OP enable Digital I/O power, 3.3V
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
33
EP7309 High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 Name DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR WRITE EXPRDY VSSIO VDDIO nCS[2] nMWE N/C CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] RXD[2] PB[7] TDI WORD VSSIO nCS[0] Type O O Description LCD serial display data LCD line clock
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location E7 E8 E9 E10 E11 E12 Name N/C FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/nBROM VDDIO D[9] D[10] PB[5] PB[3] VSSIO TXD[2] RUN/CLKEN VSSIO N/C DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO PB[1]/PRDY[2] VDDIO TDO PB[4] PB[6] VSSRTC VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] PA[7] PA[5] VSSIO PA[4] PA[6] Type O O O I/O Oscillator ground LCD frame synchronization pulse System byte address Data I/O PLL ground Description
Core power Digital core power, 2.5V I/O O O O I Pad power I Pad power I Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground I I O I Pad ground Pad power O O O O LCD pixel clock out Data I/O System byte address System byte address
Pad ground I/O ground I Pad power I/O I/O I I Media change interrupt input / internal rom boot enable Digital I/O power, 3.3V Data I/O Data I/O GPIO port B GPIO port B
System byte address System wake up input Digital I/O power, 3.3V User reset input Digital I/O power, 3.3V Expansion clock input I/O ground Digital I/O power, 3.3V I/O ground I/O ground I/O ground Digital I/O power, 3.3V I/O ground I/O ground I/O ground Digital I/O power, 3.3V I/O ground I/O ground Power-on reset input External power supply sense input Transfer direction Expansion port ready input I/O ground Digital I/O power, 3.3V Chip select out ROM, expansion write enable G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 Pad power O I I E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1
Pad ground I/O ground O O UART 2 transmit data output Run output / clock enable output
Pad ground I/O ground O O O I/O LCD serial display data System byte address Data I/O
RTC ground Real time clock ground I I Battery ok input Battery changed sense input
Pad ground I/O ground I/O Pad power I Data I/O Digital I/O power, 3.3V GPIO port B / CL-PS6700 interface signal Digital I/O power, 3.3V JTAG data out GPIO port B GPIO port B
Core ground Real time clock ground RTC ground Real time clock ground O I/O LCD serial display data Data I/O
Core ground Real time clock ground I/O I I Pad power Pad ground I/O I/O I I I O Pad ground O Data I/O Power fail sense input Main oscillator input Digital I/O power, 3.3V I/O ground Data I/O Data I/O UART 2 receive data input GPIO port B JTAG data input Word access select output I/O ground Chip select out
RTC ground Real time clock ground O O O System byte address System byte address System byte address
Pad ground I/O ground I/O I/O I I Data I/O Data I/O GPIO port A GPIO port A
Pad ground I/O ground I I GPIO port A GPIO port A
34
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 Name PB[0]/PRDY[1] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13] VSSIO D[14] D[15] PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17] A[16] A[15] A[14] nTRST D[16] D[17] LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO RXD[1] DSR VDDIO nEINT[1] PE[2]/CLKSEL Type I I Description GPIO port B / CL-PS6700 interface signal GPIO port B L8 RTC ground Real time clock ground L9 RTC ground Real time clock ground L10 O O O O Pad ground I/O I/O I I Pad ground I I O I System byte address L11 System byte address L12 System byte address L13 System byte address L14 I/O ground L15 Data I/O L16 Data I/O M1 GPIO port A M2 GPIO port A M3 I/O ground M4 GPIO port A M5 GPIO port A M6 UART 1 transmit data out M7 UART 1 clear to send input M8 RTC ground Real time clock ground M9 RTC ground Real time clock ground M10 O O O O I I/O I/O O I Pad ground I I I System byte address M11 System byte address M12 System byte address M13 System byte address M14 JTAG async reset input M15 Data I/O M16 Data I/O N1 IR LED drivet N2 Photodiode input N3 I/O ground N4 UART 1 data carrier detect N5 Test mode select input N6 External interrupt N7 RTC ground Real time clock ground N8 I O I I/O I/O I/O Pad ground Pad power Pad power I I Pad power I I SSI1 ADC serial input N9 Keyboard scanner column drive N10 JTAG clock N11 Data I/O N12 Data I/O N13 Data I/O N14 I/O ground N15 Digital I/O power, 3.3V N16 Digital I/O power, 3.3V P1 UART 1 receive data input P2 UART 1 data set ready input P3 Digital I/O power, 3.3V P4 External interrupt input P5 GPIO port E / clock input mode select VDDIO Pad power Digital I/O power, 3.3V VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground RTCOUT O Real time clock oscillator output VSSRTC RTC ground Real time clock ground D[23] I/O Data I/O D[22] I/O Data I/O VSSIO Pad ground I/O ground HALFWORD O Halfword access select output D[26] I/O Data I/O D[29] I/O Data I/O COL[2] O Keyboard scanner column drive SMPCLK O SSI1 ADC sample clock ADCCLK O SSI1 ADC serial clock SSIRXDA I/O DAI/CODEC/SSI2 serial data input PD[2] I/O GPIO port D PD[5] I/O GPIO port D VDDIO Pad power Digital I/O power, 3.3V VSSIO Pad ground I/O ground PE[1]/BOOTSEL[1] I GPIO port E / boot mode select nEXTFIQ I External fast interrupt input D[21] I/O Data I/O A[20] O System byte address VDDIO Pad power Digital I/O power, 3.3V A[23] O System byte address VSSIO Pad ground I/O ground D[27] I/O Data I/O COL[0] O Keyboard scanner column drive FB[0] I PWM feedback input DRIVE[1] I/O PWM drive output SSITXFR I/O DAI/CODEC/SSI2 frame sync VDDIO Pad power Digital I/O power, 3.3V TMS I JTAG mode select PE[0]/BOOTSEL[0] I GPIO port E / Boot mode select VDDIO Pad power Digital I/O power, 3.3V nEINT[2] I External interrupt input nTEST[0] I Test mode select input A[19] O System byte address A[18] O System byte address VSSIO Pad ground I/O ground A[21] O System byte address A[22] O System byte address VSSRTC RTC ground Real time clock ground D[31] I/O Data I/O COL[6] O Keyboard scanner column drive VSSRTC Core ground Real time clock ground
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location L6 L7 Name VSSRTC PD[0]/LEDFLSH Type Description
RTC ground Real time clock ground I/O GPIO port D / LED blinker output
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
35
EP7309 High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Name VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27] A[25] VDDIO A[24] VDDRTC PD[7] PD[6] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26] D[25] VSSIO Type Pad ground Pad ground Pad power Pad ground Pad power Pad ground Pad ground Pad power Pad ground I/O Pad power I/O Pad power I/O I/O O O Pad power O O O O I/O O O Pad power O RTC power I/O I/O I/O I/O - I/O ground I/O ground Digital I/O power, 3.3V I/O ground Digital I/O power, 3.3V I/O ground I/O ground Digital I/O power I/O ground Data I/O Digital I/O power, 3.3V Real time clock oscillator input Digital I/O power, 3.3V GPIO port D GPIO port D DAI/CODEC/SSI2 serial data output SSI1 ADC chip select Digital I/O power, 3.3V SSI1 ADC serial data output Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Data I/O System byte address System byte address Digital I/O power, 3.3V System byte address Real time clock power, 2.5V GPIO port D GPIO port D GPIO port D DAI/CODEC/SSI2 serial clock DAI/CODEC/SSI2 frame sync Description
Core power Core power, 2.5V I/O I O Pad power O I/O O I/O Pad ground PWM drive output PWM feedback input Keyboard scanner column drive Digital I/O power, 3.3V Buzzer drive output Data I/O System byte address Data I/O I/O ground
36
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table V. JTAG Boundary Scan Signal Ordering
LQFP Pin No.
1 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43
TFBGA Ball
B3 A2 B1 E3 C1 C2 E2 D2 F3 D1 F2 G3 E1 F1 G2 G1 H3 H1 J3 J2 J1 L3 K2 K1 M3 L2 L1 N3 M2 M1 P3 N1 N2 R3 P1 P2
PBGA Ball
B1 C2 E4 D1 F5 D2 F4 E1 E2 G5 F1 G4 F2 H7 G1 H6 H1 H5 H2 H4 J1 J4 J2 J5 K1 J6 K2 J7 L1 K4 L2 K5 M1 K6 M2 L4
Signal
nCS[5] EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY2 PB[0]/PRDY1 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN CTS RXD1 DCD DSR nTEST1 nTEST0 EINT3 nEINT2 nEINT1
Type
O I/O O O O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I I I I I I I
Position
1 3 6 8 10 13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67 69 70 71 72 73 74 75 76 77 78
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
37
EP7309 High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
44 45 46 47 53 54 55 56 59 60 61 62 68 69 70 75 76 77 78 79 80 82 83 84 85 86 87 88 91 92 93 94 95 96 97 99 100 101
TFBGA Ball
T3 R1 R2 T1 T2 V4 W4 Y4 V5 W5 Y5 V6 W6 Y6 W8 Y8 V9 W10 Y10 V11 W11 Y11 Y12 W12 V12 Y13 W13 V13 Y14 W14 A1 V14 Y15 W15 V15 Y16 W16 V16
PBGA Ball
N1 L5 N2 M4 T2 T3 N5 R3 T4 N6 R4 L7 T6 K8 R6 M8 T8 N8 R8 N9 T9 M9 R9 L9 T10 K9 R10 N10 R11 M10 T12 L10 R12 N11 T13 R13 M11 T14
Signal
nEXTFIQ PE[2]/CLKSEL PE[1]/BOOTSEL1 PE[0]/BOOTSEL0 PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27] D[27] A[26]
Type
I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I O I/O I/O O O O I I O O O O O O O O O I/O I/O I/O I/O Out I/O O
Position
79 80 83 86 89 92 95 98 101 104 107 110 122 125 126 128 131 134 136 138 140 141 142 144 146 148 150 152 154 156 158 160 163 166 169 172 174 177
38
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
102 103 104 105 106 109 110 111 112 113 114 115 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 141 142 143 144 145 146 147
TFBGA Ball
Y17 W17 Y18 V17 W18 Y19 W20 U18 V20 U19 U20 T19 T20 R19 R20 T18 P19 P20 R18 N19 N20 P18 M19 N18 L20 L19 M18 K20 K19 K18 J20 J19 H20 H19 J18 K3 Y3 G20
PBGA Ball
N12 R14 T15 N13 R16 P15 M13 N16 L12 N15 L13 M16 M15 K11 L16 K12 L15 K13 J10 J16 J11 J15 J12 H16 J13 H15 H13 G16 H12 G15 H11 F15 H10 E16 G13 E15 G12 D16
Signal
D[26] A[25] D[25] HALFWORD A[24] D[24] A[23] D[23] A[22] D[22] A[21] D[21] A[20] D[20] A[19] D[19] A[18] D[18] A[17] D[17] A[16] D[16] A[15] D[15] A[14] D[14] A[13] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8]
Type
I/O O I/O O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O
Position
179 182 184 187 189 191 194 196 199 201 204 206 209 211 214 216 219 221 224 226 229 231 234 236 239 241 244 246 249 251 254 256 259 261 264 266 269 271
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
39
EP7309 High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 186 187 188 189 191 192 193 194 195 196 199 200
TFBGA Ball
H18 F20 G19 E20 F19 G18 D20 F18 D19 E19 C19 C20 E18 B20 B16 A16 C15 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 C11 B11 B10 A10 A9 B9 C9 A8 B8 C8
PBGA Ball
G11 D15 F13 C16 F12 C15 E13 B16 B14 D11 A13 F10 B13 E10 B12 D10 A11 G9 B11 A10 F9 B10 E9 A9 D8 B8 E8 A7 F8 B7 A6 G8 B6 D7 A5 E7 F7 A4
Signal
A[7] D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/nBROM nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] N/C N/C N/C N/C N/C N/C
Type
O I/O I I I I I I I I O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O O I/O I/O I/O I/O O O I/O I/O I/O I/O
Position
274 276 279 280 281 282 283 284 285 286 287 289 292 294 297 299 302 304 307 309 312 314 317 319 322 324 326 328 330 333 336 339 342 344 346 349 352 355
40
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
201 202 204 205 206 207 208
TFBGA Ball
A7 B7 C7 A6 B6 C6 A5
PBGA Ball
D6 B4 E6 A3 D5 B3 A2
Signal
nMWE nMOE nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
Type
O O O O O O O
Position
358 360 362 364 366 368 370
1) See EP7309 Users' Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
41
EP7309 High-Performance, Low-Power System on Chip
CONVENTIONS
This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.
Table W. Acronyms and Abbreviations (Continued)
Acronym/ Abbreviation
TAP TLB
Definition
test access port translation lookaside buffer universal asynchronous receiver
Acronyms and Abbreviations
Table W lists abbreviations and acronyms used in this data sheet.
Table W. Acronyms and Abbreviations
UART
Units of Measurement
Table X. Unit of Measurement
Acronym/ Abbreviation
A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI
Definition
analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow (9600-115.2 kbps) infrared static random access memory synchronous serial interface
Symbol
Unit of Measure
degree Celsius sample frequency hertz (cycle per second) kilobits per second kilobyte (1,024 bytes) kilohertz kilohm megabits (1,048,576 bits) per second megabyte (1,048,576 bytes) megabytes per second megahertz (1,000 kilohertz) microampere microfarad microwatt microsecond (1,000 nanoseconds) milliampere milliwatt millisecond (1,000 microseconds) nanosecond volt watt
C
fs Hz kbps KB kHz k Mbps MB MBps MHz
A F W s
mA mW ms ns V W
42
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309 High-Performance, Low-Power System on Chip
General Conventions
Hexadecimal numbers are presented with all letters in uppercase and a lowercase "h" appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an "h", 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7309 User's Manual. The use of "TBD" indicates values that are "to be determined," "n/a" designates "not available," and "n/c" indicates a pin that is a "no connect."
Pin Description Conventions
Abbreviations used for signal directions are listed in Table Y.
Table Y. Pin Description Conventions
Abbreviation
I O I/O Input Output Input or Output
Direction
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
43
EP7309 High-Performance, Low-Power System on Chip
ORDERING INFORMATION
The order number for the device is:
EP7309 -- CV -- C
Revision Package Type: V = Low Profile Quad Flat Pack B = Plastic Ball Grid Array (17 mm x 17 mm) R = Reduced Ball Grid Array (13 mm x 13 mm) Part Number Product Line: Embedded Processor Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version
Note:
Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
44
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
* Notes *

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